The present invention relates to a semiconductor device. To be more specific, the present invention relates to logic and memory circuits using field-effect transistors (FETs) and double hetero junction bipolar transistors (DHBTs) having different polarities from each other. In particular, the present invention relates to a semiconductor device which has a two-dimensional electron gas base having, in its base and collector, a double hetero junction structure allowing a pnp-type HBT and an n-channel FET both implemented at the same time on the same multilayer structure, and is suitable for use as a complementary BiFET having an ultra-high speed and ultra-low power consumption.
In circuit conventional integrated logic circuits and integrated memory circuits which have a generic name IC standing for an integrated circuit, bipolar and field-effect transistors are used. In general, an integrated circuit using bipolar transistors offers a characteristic of having a large load drivability and a high speed. On the other hand, an integrated circuit using field-effect transistors exhibits a characteristic of having a high integration density and low power consumption. In particular, most semiconductor devices made of silicon are CMOS (Complementary MOS) logic circuits using n and p-type MOS (Metal Oxide Semiconductor) FETs. A large number of MOSFETs can be used due to their property of consuming only low power. Several hundreds of thousands of gates constituting large-scale logic circuits can be formed on a single LSI silicon chip, being embedded in an area of the order of one square centimeter. As a result of an application of the CMOS technology to memory products, four-megabit SRAMS (Static Random-Access Memories) with an access time of 15 nanoseconds and low power consumption of less than 1 W have been successfully implemented. From the device-structure point of view, the successful implementation of the four-megabit SRAMS is attributed to the successful development of a technology which allows n- and p-channel MOSFETS to be created with a high degree of stability.
In the case of a bipolar-transistor IC, on the other hand, a carrier-storage phenomenon occurring in a saturation region is observed. When used as a high-speed logic circuit, it is thus necessary to operate the bipolar transistor in a non-saturation region. When thinking about only the principle of operation, the DCTL (Direct Coupled Transistor Logic) was also taken as a subject of a feasibility study. However, the transistor inevitably operates in the saturation region, resulting in a low speed. As an IC, the DCTL can thus hardly be put to practical use. As a result, a circuit type that allows the transistors in the non-saturation region cited above is adopted. That is, most bipolar transistors in use are of the current-switching types such as the CML (Current Mode Logic) and the ECL (Emitter Coupled Logic) which allow the bipolar transistors to operate in the non-saturation region.
In order to increase the LSI speed of a bipolar-transistor integrated circuit, an ECL (Emitter Coupled Logic) circuit, is preferably used. In this case, the circuit is used by continuously flowing the emitter current all the time. Accordingly, it consumes much power. As a result, large-scale integration can not be implemented. In the following description, an ECL circuit is taken as an example. An example of the highest level of integration is the so-called 64-kilobit SRAM with power consumption of 20 W and a short access time of the order of 2 nanoseconds. A typical CMOS device is therefore 100 times better in terms of integration level and power consumption. Since the levels of integration are much different from each other, however, the comparison of an ECL device to a CMOS device is not a fair comparison. Nevertheless, a bipolar-transistor integrated circuit is superior in that its speed is higher by 10 times as much.
In order to increase the speeds of systems developed in recent years, nevertheless, high-speed LSI devices are in high demand. As a result, the superiority of a circuit using bipolar transistors starts threatening the dominance of the BiCMOS and CMOS devices.
In addition, personal communication equipment such as personal computers with radio-communication functions and radio LANS for transmission of information in the high-frequency region of the order of 1 to 30 GHz are in high demand in the telecommunication area. Thus, low-power transistors and circuits offering power consumption of the order of 10 mW, which can cope with problems encountered in such a high-frequency region, are required. Basically, devices with ultra-low powers and ultra-high speeds are really expected as devices of the next stage.
In the case of the CMOS technology, on the other hand, performance improvement resulting from the miniaturization of the gate length does not make any further progress as suggested by the original trend. Furthermore, it is also necessary to decrease the supply voltage from 5 V to a value in the range 2.0 to 3.3 V in order to preserve reliability. Accordingly, the load drivability of the transistor deteriorates, resulting in a reduced LSI speed.
During the 1980s decade, on the other hand, IC devices with an ultra-high speed using compound semiconductors as their raw materials were developed. Gallium arsenic is a representative example of such compound semiconductor materials. The gallium-arsenic compound semiconductor material has a mobility six times that of silicon and can thus be used as a semi-insulating substrate. Devices, which were made up of gallium arsenic, were at that time field-effect transistors (FETs) such as GaAs MESTETs and HEMTs (High Electron Mobility Transistors) to mention a few. The so-called SCFL (Source Coupled FET Logic) similar to the ECL described above and the DCFL (Direct Coupled FET Logic) using enhancement and depletion-type FETs are predominant types of circuits. The GaAs FET is about the same as the silicon bipolar transistor as far as the level of integration and the speed are concerned. However, the former exhibits characteristics of being capable of reducing power consumption to about one-third in comparison to that of the latter and generating low noise at high frequencies. A complementary circuit making use of n- and p-channel FETs in a GaAs FET is described, for example, on Pages 317 to 320 of an IEEE IEDM abstract issued in the year of 1985. A detailed study of the circuit performance is discussed on Pages 1889 to 1896 of the IEEE Transactions ED-34, 1987 or on Page 262 of the IEEE Electron Device Letters EDL8 No. 6 in year of 1957.
However, these conventional technologies have shortcomings that the performance of the p-channel FET cannot be improved and a high speed, which is the most important characteristic of the compound semiconductor material, cannot be realized. The mobility of a two-dimensional hole gas at the AlGaAs/GaAs hetero junction is 400 cm.sup.2 /Vs at room temperature. As for the FET performance, the transconductance Gm is 170 mS/mm at a gate length Lg of 0.1 .mu.m and a source-gate resistance Rsg of 1.7 .OMEGA.mm. Refer to, for example, the description on Pages 716 to 723 and FIG. 1(a) of the Transactions of the Institute of Electronics, Information and Communication Engineers, C, Vol. J70-C, No. 5, May 1987. This FET performance can be expected to be about merely one-seventh of the n-channel FET and, therefore, there is no way of achieving a high speed. From the power-consumption point of view, the gate electrode of either the n or p channel experiences a high forward bias when the circuit is at a standby state due to the fact that the so-called Shottky junction is adopted in the gate structure, causing the gate current to flow from the power supply to the ground side and consuming almost 80% or even more of the total consumed power of the circuit as is generally known. On the contrary, the conventional CMOS device has a characteristic of consuming power only while the circuit is switching from one state to another. Accordingly, the important feature of a complementary circuit of GaAs FET of consuming only low power is lost.
In the case of a hetero bipolar transistor (abbreviated as an HBT) which is made up of compound semiconductor materials, on the other hand, using the same circuit as that of the silicon bipolar transistor such as the ECL circuit results in a shortcoming that the turned-on power of the hetero bipolar transistor increases to 1.5 times, giving rise to twice as much consumed power due to a large band gap.
That is, with FETs and bipolar transistors made up of the conventional compound semiconductor materials, a device that implements an ultra-high speed smaller than a propagation time of 10 psec per gate and ultra-low consumed power less than 10 .mu.W at the same time could not so far be created.